1. Field of Invention
The invention relates to an I/O (Input/Output) buffer circuit. More particular, the invention pertains to an I/O buffer circuit with variable conductivity, which can improve the data integrity and decrease signal wave deformation during SSO (Simultaneous Switching Output).
2. Related Art
With reference to FIG. 1, the conventional I/O buffer circuit is a push-pull driver comprised of a PMOS (P-type Metal Oxide Semiconductor) transistor T1 and an NMOS (N-type Metal Oxide Semiconductor) transistor T2. The transistors T1 and T2 are connected between a work voltage Vdd and the ground Gnd in series. The input signal Vi passes through two NOT gates 13 to reach the gates of the transistors T1 and T2. The drains of the transistors T1 and T2 are both connected to the output terminal pad, output signal Vo. When the input signal Vi has a Hi voltage, it is inverted by the NOT gate 13 into a Lo voltage. The transistor T1 called a pull-up transistor becomes conductive while the transistor T2 cuts off. The output signal Vo is thus Hi voltage. On the contrary, when the input signal Vi has a Lo voltage, the transistor T2 called a pull-down transistor becomes conductive while the transistor T1 cuts off. Therefore, the output signal Vo is Lo voltage.
In a VLSI (Very Large Scale Integrated) circuit, the so-called SSO refers to the simultaneous transition of the output signals from two or more I/O buffers. When the SSO appears, the internal power Vdd′ and the ground Gnd′ of the VLSI circuit may produce power bounce and ground bounce. Such noise signal produced by the SSO will cause incorrect judgment on data levels by the receiver. The power bounce and ground bounce often result from simultaneous transitions on a plurality of output signals of the I/O buffers from Hi to Lo or vice versa.
FIG. 2 shows an equivalent circuit of a VLSI internal I/O buffer bus. As shown in the drawing, the internal power Vdd′ and the ground Gnd′ of the VLSI circuit are connected with an external power Vdd and an external ground Gnd through protector inductors L1 and L2, respectively. In the I/O buffer bus, one I/O port D1 is maintained at Hi while another I/O port D2 at Lo. The rest of I/O ports may have Hi level or Lo level. When the SSO occurs, the internal power Vdd′ and the ground Gnd′ will generate a larger load current i. When the load current flows through the inductors L1 and L2, the outputs Hi level Vdd and Lo level Gnd from the I/O ports D1 and D2 become unstable due to power bounce and ground bounce caused by the voltage drops of the inductors L1 and L2, affecting the accuracy of data reception.
Let's further explain the power bounce phenomenon occurring to the I/O port D1 with reference to FIG. 3A. It shows an equivalent circuit of the I/O port D1 in FIG. 2 and the signal waveform at the receiving end. When the input signals of the rest of I/O port bus change from Lo to Hi, the internal power Vdd′ of the VLSI circuit has a load current i1 going to the receiving end. This load current produces a voltage drop L1(di1/dt) on the inductor L1, so that the Hi level Vdd of the I/O port D1 produces a maximal undershooting oscillation (as shown on the right-hand side of FIG. 3A). In response to this phenomenon, the voltage RA at the receiving end also drops. Therefore, the voltage level at the receiving end may be determined incorrectly as Lo instead of Hi. Such incorrect determinations and actions will affect the normal operations of the circuit.
We use FIG. 3B to further explain the ground bounce phenomenon occurring to the I/O port D2. It shows an equivalent circuit of the I/O port D2 in FIG. 2 and the signal waveform at the receiving end. When the input signals of the rest of I/O port bus change from Hi to Lo, the internal ground Gnd′ of the VLSI circuit draws a load current i2 from the receiving end. This load current produces a voltage increase L2(di2/dt) on the inductor L2, making the I/O port D2 outputs a Lo level voltage (as shown on the right-hand side of FIG. 3B). In response to this phenomenon, the voltage RB at the receiving end produces a bounce. Therefore, the voltage level at the receiving end may be determined incorrectly as Hi instead of Lo. Such incorrect determinations and actions also affect the normal operations of the circuit.